This invention relates to a system having a controller and a memory and, more particularly, to a data sending/receiving operation between the controller and the memory.
In a conventional data sending/receiving operation between the controller and the memory, either the controller or the memory who serves as a sender generates a data strobe signal which is synchronized with a clock signal. Data signals are sent out from the sender is synchronized with the data strobe signal as disclosed in U.S. Pat. No. 6,789,209B1, Description of the Related Art, the contents of U.S. Pat. No. 6,789,209B 1 being incorporated herein by reference in their entireties.
U.S. Pat. No. 6,789,209B1 points out some problems on the use of the data strobe signal and, alternative to the data strobe signal, proposes a system which sends/receives the data in synchronization with the clock signal.